Design of a CMOS Integrated Circuit for an 8-to-3 Line Priority Encoder. Científica, [S. l.], v. 29, n. 2, p. 1–14, 2025. DOI: 10.46842/ipn.cien.v29n2a06. Disponível em: https://cientifica-ipn.com/index.php/esime/article/view/192. Acesso em: 7 nov. 2026.