Design of a CMOS Integrated Circuit for an 8-to-3 Line Priority Encoder

Abstract

The aim of this work is the design of a priority encoder in an integrated circuit (IC) with CMOS technology, based on the Texas Instruments (TI) 74LS148 chip. This digital circuit is widely used, especially in the design of digital systems and microprocessors. Its main function is to convert multiple active inputs into a representative binary output, hierarchically prioritizing the inputs. It is considered a fundamental building block, due to its ability to handle multiple events simultaneously and decide which one should be attended to first. The proposed chip was designed using the L-Edit tool from Mentor Graphics, along with all the necessary calculations to determine both channel width (W) and length (L) of the designed transistors, to implement a decoder IC with lower power consumption and a wider operating range. furthermore CMOS (complementary metal-oxide-semiconductor) technology is based on field-effect transistors, which, over time, have gained popularity in integrated circuits (ICs). Its main features are low power consumption, switching speed and high noise immunity.